Browse by author
Lookup NU author(s): Nor Mahyuddin, Dr Gordon Russell
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but results in increase of power dissipation. Subsequently, other alternatives are considered. The impact of transistor sizes and temperature on SEU tolerance is tested. Results indicate no significant changes in Q(crit) when the effective transistor length is increased by 10%, but there is an improvement when high temperature and high bias currents are applied. However, this is due to other process parameters that are temperature dependent, which contribute to the sharp increase in Q(crit). It is found that, with temperature, there is no clear factor that can justify the direct impact of temperature on the SEU tolerance. Thus, in order to improve the SEU tolerance, high bias currents are still considered to be the most effective method in improving the SEU sensitivity. However, good trade-off is required for the low-swing driver in order to meet the reliability target with minimal power overhead.
Author(s): Mahyuddin NM, Russell G
Publication type: Article
Publication status: Published
Journal: Scientific World Journal
Year: 2014
Pages: 1-7
Print publication date: 19/03/2014
ISSN (print): 1537-744X
ISSN (electronic): 2307-9037
Publisher: Hindawi Publishing Corporation
URL: http://dx.doi.org/10.1155/2014/876435
DOI: 10.1155/2014/876435
Altmetrics provided by Altmetric
