Asynchronous FPGA Architecture with Distributed Control

  1. Lookup NU author(s)
  2. Dr Delong Shang
  3. Dr Fei Xia
  4. Professor Alex Yakovlev
Author(s)Shang D, Xia F, Yakovlev A
Editor(s)
Publication type Conference Proceedings (inc. Abstract)
Conference Name2010 IEEE International Symposium on Circuits and Systems
Conference LocationParis, France
Year of Conference2010
Legacy Date30 May - 2 June 2010
Volume
Pages1436-1439
ISBN9781424453085
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Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possible, whilst achieving delay insensitivity in the inter-cell interconnects. By using David Cells as the central technique in the delay insensitive clock replacement, this method is conducive to the establishment of an automatic design and synthesis flow. It also particularly caters for low power designs, where current FPGA solutions are not effective yet.
PublisherIEEE
URLhttp://dx.doi.org/10.1109/ISCAS.2010.5537316
DOI10.1109/ISCAS.2010.5537316
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