Browse by author
Lookup NU author(s): Professor Paul WatsonORCiD
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
This paper discusses the problems of implementing a parallel machine architecture to support graph reduction. In particular it examines the area of memory organization and the mechanisms which are required to ensure that the full benefits of this implementation strategy are maintained whilst achieving an efficient physical structure. The major areas of interest are the maintenance of locality and the use of storage management techniques which minimize communication.
Author(s): Watson I, Watson P
Editor(s): Fasel, J.H., Keller, R.M.
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Graph Reduction Workshop
Year of Conference: 1987
Pages: 265-274
ISSN: 0302-9743 (Print) 1611-3349 (Online)
Publisher: Springer
URL: http://dx.doi.org/10.1007/3-540-18420-1_60
DOI: 10.1007/3-540-18420-1_60
Library holdings: Search Newcastle University Library for this item
Series Title: Lecture Notes in Computer Science
ISBN: 9783540184201
