Asynchronous Microprocessors: From High Level Model to FPGA Implementation

  1. Lookup NU author(s)
  2. Keith Heron
  3. Dr Albert Koelmans
  4. Professor Alex Yakovlev
Author(s)Lloyd L, Heron K, Koelmans AM, Yakovlev A
Publication type Report
Series TitleDepartment of Computing Science Technical Report Series
Year1997
DateSeptember 1997
Report Number610
Pages23
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In order to determine the applicability of both programmable software tools and programmable hardware for asynchronous logic applications an implementation, employing FPGA devices, of the instruction decode and the instruction execution stages of an asynchronous microprocessor, the ADLX, is presented. The foundation for that microprocessor is based on the employment of event driven logic, specifically 2-phase transition signalling, that functions within the conceptual framework of a Sutherland micropipeline. The entire design has been constructed from a series of VHDL descriptions that have been compiled and simulated using both the Cypress WARP VHDL Development System and the AMD MACHXL software packages. A number of the asynchronous specific areas of the ADLX have been synthesized using Petrify, a Petri Net tool designed for the manipulation of concurrent specifications of asynchronous control circuits. The ADLX itself has been constructed from a range of "off-the-shelf" products including HM 65764 high speed CMOS SRAM semiconductors and FPGA logic devices.
InstitutionDepartment of Computing Science, University of Newcastle upon Tyne
Place PublishedNewcastle upon Tyne
URLhttp://www.cs.ncl.ac.uk/publications/trs/papers/610.pdf
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