Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design

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  2. Agnes Madalinski
  3. Dr Alex Bystrov
  4. Dr Victor Khomenko
  5. Professor Alex Yakovlev
Author(s)Madalinski A, Bystrov A, Khomenko V, Yakovlev A
Publication type Article
JournalIET Computers & Digital Techniques
Year2003
Volume150
Issue5
Pages285-293
ISSN (print)1751-8601
ISSN (electronic)1751-861X
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Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.
PublisherIEE
URLhttp://dx.doi.org/10.1049/ip-cdt:20030831
DOI10.1049/ip-cdt:20030831
NotesSpecial Issue on Best Papers from DATE'2003
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