Optimisation of Balsa control path using STG resynthesis

  1. Lookup NU author(s)
  2. Arseniy Alekseyev
  3. Ivan Poliakov
  4. Dr Victor Khomenko
  5. Professor Alex Yakovlev
Author(s)Alekseyev A, Poliakov I, Khomenko V, Yakovlev A
Editor(s)Yakovlev, A.
Publication type Conference Proceedings (inc. Abstract)
Conference Name21st UK Asynchronous Forum
Conference LocationBristol, UK
Year of Conference2009
Legacy Date14-15 September 2009
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
The paper proposes a modification of the standard design workflow that is used in Balsa design automation system. The controllers obtained by syntax-directed mapping used in Balsa usually suffer from performance, area and power overheads because the predesigned set of components is required to implement the declared protocols fully and correctly in order to be reusable in all possible circuit configurations, which results in redundancy. This redundancy can be eliminated by replacing the manually designed gate-level implementations of the high level components with the corresponding STG specifications. The STGs of individual components that form the system are then composed together to produce the final system STG that is used to synthesise an optimal implementation of the control circuit. The process is automated as a plug-in to Workcraft framework.
PublisherComputer Science Department, University of Bristol