Logic Decomposition of Asynchronous Circuits Using STG Unfoldings

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  2. Dr Victor Khomenko
Author(s)Khomenko V
Editor(s)Bainbridge, J., Jones, I.
Publication type Conference Proceedings (inc. Abstract)
Conference Name17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Conference LocationCornell University, Ithaca, New York, USA
Year of Conference2011
Date27-29 April 2011
Volume
Pages3-12
Series Editor(s)17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
ISBN9781612849737
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A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilisation and highly optimised circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory consumption and runtime.
PublisherIEEE
URLhttp://dx.doi.org/10.1109/ASYNC.2011.10
DOI10.1109/ASYNC.2011.10
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