Logic Decomposition of Asynchronous Circuits Using STG Unfoldings
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- Dr Victor Khomenko
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| Author(s) | | Khomenko V |
| Editor(s) | | Bainbridge, J., Jones, I. |
| Publication type | | Conference Proceedings (inc. Abstract) |
| Conference Name | | 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) |
| Conference Location | | Cornell University, Ithaca, New York, USA |
| Year of Conference | | 2011 |
| Date | | 27-29 April 2011 |
| Volume | | |
| Pages | | 3-12 |
| Series Editor(s) | | 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) |
| ISBN | | 9781612849737 |
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| Full text for this publication is not currently held within this repository. Alternative links are provided below where available. |
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| A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilisation and highly optimised circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory consumption and runtime. |
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| Publisher | | IEEE |
| URL | | http://dx.doi.org/10.1109/ASYNC.2011.10 |
| DOI | | 10.1109/ASYNC.2011.10 |
| Actions | |  |
| Library holdings | | Search Newcastle University Library for this item |
