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Lookup NU author(s): Professor Raj Ranjan
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© 2016 Elsevier Inc.As VLSI technology advances towards nanoscale devices, interconnect delay is becoming increasingly important, and could be effectively reduced using buffer insertion. The widely-used buffer insertion technique in industry is to insert a set of buffers on the chip, which may overlap some gates, and then greedily move the buffers to the nearest available buffer holes. The moving distance of inserted buffers largely affects the wirelength which may result in the increase of the interconnect delay. This necessitates efficient algorithms to minimize the moving distance of buffers for effective buffer insertion to obtain high-performance VLSI designs. This paper proposes an efficient, perturbation constrained buffer planning algorithm to maximize the candidate buffer holes with regarding to the feature of CPS based buffering design framework. Instead of directly moving buffers to the existing available buffer holes, the proposed algorithm changes the original placement by moving some gates tinily to provide more flexibility for buffer insertion. The integer linear programming based technique is designed for the physical design flow which allows small moving range of gates. Parallel technique is utilized to solve the ILP problems efficiently when the scale of chip is increasing. Experimental results have shown that the proposed algorithm achieves at most 41.49% increase in the available buffer holes when compared to the algorithm with no gate movement.
Author(s): Chen X, Huang X, Xiang Y, Zhang D, Ranjan R, Liao C
Publication type: Article
Publication status: Published
Journal: Journal of Parallel and Distributed Computing
Year: 2017
Volume: 103
Pages: 3-10
Print publication date: 01/05/2017
Online publication date: 20/12/2016
Acceptance date: 23/11/2016
ISSN (print): 0743-7315
Publisher: Academic Press Inc.
URL: https://doi.org/10.1016/j.jpdc.2016.11.013
DOI: 10.1016/j.jpdc.2016.11.013
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