Language and Hardware Acceleration Backend for Graph Processing

  1. Lookup NU author(s)
  2. Dr Andrey Mokhov
  3. Alessandro De Gennaro
  4. Dr Ghaith Tarawneh
  5. Serhii Mileiko
  6. Professor Alex Yakovlev
Author(s)Mokhov A, De Gennaro A, Tarawneh G, Wray J, Lukyanov G, Mileiko S, Scott J, Yakovlev A, Brown A
Editor(s)
Publication type Conference Proceedings (inc. Abstract)
Conference NameFDL 2017 Forum on specification & Design Languages
Conference LocationVerona, Italy
Year of Conference2017
Source Publication Date
Volume
Pages
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Graphs are important in many applications however their analysis on conventional computerarchitectures is generally inefficient because it involves highly irregular access tomemory when traversing vertices and edges. As an example, when finding a path from a sourcevertex to a target one the performance is typically limited by the memory bottleneck whereasthe actual computation is trivial.This paper presents a methodology for embedding graphs into silicon, where graph verticesbecome finite state machines communicating via the graph edges. With this approach many commongraph analysis tasks can be performed by propagating signals through the physical graph andmeasuring signal propagation time using the on-chip clock distribution network. This eliminatesthe memory bottleneck and allows thousands of vertices to be processed in parallel.We present a domain-specific language for graph description and transformation, and demonstratehow it can be used to translate application graphs into an FPGA board, where they can beanalysed 1000x faster than on a conventional computer cluster.
PublisherFDL
URLhttps://ecsi.org/fdl
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