Multiple carries prediction to enhance the performance of a 32-bit estimated carry adder

  1. Lookup NU author(s)
  2. Esmail Ashmila
  3. Professor Satnam Dlay
  4. Emeritus Professor Oliver Hinton
Author(s)Ashmila EM, Dlay SS, Hinton OR
Editor(s)
Publication type Conference Proceedings (inc. Abstract)
Conference NameCommunication Systems, Networks and Digital Signal Processing (CSNDSP)
Conference LocationUniversity of Northumbria, Newcastle upon Tyne, UK
Year of Conference2004
Legacy Date20-22 July 2004
Volume
Pages617-620
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This paper presents a novel methodology to significantly improve the speed performance of a 32 bit estimated carry (ESTC) adder and extends the theory of the ESTC adder, and shows that further performance benefits can be achieved by using the statistical approach together with multiple carries. The simulation results for multiple carries, shows that the 32-bit adder can achieve dramatic speed advantages over other adders. Furthermore, the comparison in term of delay-area product shows a saving of 44.2% over a ripple adder, 41% over carry select adder; with ripple adder elements, and over 26% on carry select look-ahead adders. (12 References).
NotesDlay SS Newcastle upon Tyne, UK. Communication Systems, Networks and Digital Signal Processing. CSNDSP 2004. Fourth International Symposium. Newcastle upon Tyne, UK. 20-22 July 2004.