Design of sub-10-picoseconds on-chip time measurement circuit

  1. Lookup NU author(s)
  2. Mohd Abas
  3. Dr Gordon Russell
  4. Professor David Kinniment
Author(s)Abas MA, Russell G, Kinniment DJ
Publication type Conference Proceedings (inc. Abstract)
Conference NameDesign, Automation and Test in Europe Conference and Exhibition. IEEE Comput. Soc. Part Vol.2, 2004
Conference LocationParis, France
Year of Conference2004
Legacy Date16-20 February 2004
Pages804-9 Vol
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The rapid pace of change in IC technology, specifically in speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of system-on-chip (SOC) makes great demands for testing internal speed accurately as the limitation on accessing internal nodes using I/O pins becomes more difficult. This paper presents two high-resolution time measurement schemes for digital BIST applications, namely: two-delay interpolation method (TDIM) and time amplifier. The two schemes are combined to produce a completely new design for BIST time measurement which offers two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm/sup 2/ or equivalent to 3020 transistors. These two features are undoubtedly compatible with present high-speed SOC design architectures. (5 References).
PublisherIEEE Computer Society
NotesGielen G Figueras J 2. Los Alamitos, CA, USA. Proceedings. Design, Automation and Test in Europe Conference and Exhibition. Paris, France. EDAA, EDA Consortium, IEEE Comput. Soc. TTTC. IEEE Comput. Soc. DATC. ECSI. ACM/SIGDA. RAS. 16-20 Feb. 2004.
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