Modeling of the threshold voltage in strained Si/Si1-x Gex/S1-yGey(x ≥ y) CMOS architectures

  1. Lookup NU author(s)
  2. Dr Yuk Tsang
  3. Dr Sanatan Chattopadhyay
  4. Dr Suresh Uppal
  5. Dr Enrique Escobedo-Cousin
  6. Deepak Ramakrishnan
  7. Dr Sarah Olsen
  8. Professor Anthony O'Neill
Author(s)Tsang YL, Chattopadhyay S, Uppal S, Escobedo-Cousin E, Ramakrishnan HK, Olsen SH, O'Neill AG
Publication type Article
JournalIEEE Transactions on Electron Devices
Year2007
Volume54
Issue11
Pages3040-3048
ISSN (print)0018-9383
ISSN (electronic)1557-9646
Full text is available for this publication:
PublisherIEEE
URLhttp://dx.doi.org/10.1109/TED.2007.907190
DOI10.1109/TED.2007.907190
Actions    Link to this publication