A low and balanced power implementation of the AES security mechanism using self-timed circuits

  1. Lookup NU author(s)
  2. Dr Delong Shang
  3. Dr Frank Burns
  4. Dr Alex Bystrov
  5. Dr Albert Koelmans
  6. Dr Danil Sokolov
  7. Professor Alex Yakovlev
Author(s)Shang D, Burns F, Bystrov A, Koelmans A, Sokolov D, Yakovlev A
Publication type Conference Proceedings (inc. Abstract)
Conference NameIntegrated circuit and system design: power and timing modeling, optimization and simulation. 14th International Workshop, PATMOS 2004
Conference LocationSantorinim, Greece
Year of Conference2004
Source Publication Date15-17 September 2004
Series TitleLecture Notes in Computer Science
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The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional micropipelines. The pipeline stages are complex and have built-in controllers implemented as chains of David cells (special kind of latches), whose behaviour is similar to fine-grain pipelines. A highly balanced security latch is designed. The design is partly speed-independent; in a few places it uses well-localised and justified relative timing assumptions. The security properties of the system are evaluated by extensive simulation and by counting switching activity. (16 References).
NotesMacii En Paliouras V Koufopavlou O Berlin, Germany. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. 14th International Workshop, PATMOS 2004. Proceedings. Santorini, Greece. 15-17 Sept. 2004.
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