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N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures

Lookup NU author(s): Dr Sarah Olsen, Professor Anthony O'Neill, Dr Sanatan Chattopadhyay, Luke Driscoll, Dr Kelvin Kwa, Dr Jun Zhang

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Abstract

The performance of single and dual channel strained Si n-MOSFETs fabricated using CMOS process. A TEM image of the strained Si/gate oxide interface was examined. Capacitance-voltage measurement on MOS capacitor was investigated. The gate oxide interface trap density as a function of band gap energy for MOS capacitor fabricated on the single and dual channel architectures was illustrated. Field effect mobility was investigated as a function of vertical effective field on MOSFETs having 10 mu m gate lengths and 5 mu m gate widths. (6 References).

Publication metadata

Author(s): Olsen SH, O'Neill AG, Chattopadhay S, Driscoll LS, Kwa KSK, Paul DJ, Zhang J

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2003 International Semiconductor Device Research Symposium (IEEE Cat. No.03EX741). IEEE. 2003

Year of Conference: 2003

Pages: 49-50

Publisher: IEEE

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