A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability

  1. Lookup NU author(s)
  2. Nikolaos Minas
  3. Professor David Kinniment
  4. Keith Heron
  5. Dr Gordon Russell
Author(s)Minas N, Kinniment D, Heron K, Russell G
Editor(s)
Publication type Conference Proceedings (inc. Abstract)
Conference Name13th IEEE International Symposium on Asynchronous Circuits and Systems, San Francisco, March 2007
Conference LocationBerkeley, CA
Year of Conference2007
Date12-14 March 2007
Volume
Pages163-174
Series Editor(s)IEEE Computer Society
ISBN076952771X
Full text is available for this publication:
Timing issues are a major concern in the design of high performance synchronous, asynchronous circuits and GALS. Investigations into the causes of many timing problems cannot be satisfactorily undertaken using external equipment due to its remoteness from the source of the potential problem; this necessitates the development of on-chip time measurement circuitry. Current techniques have the capability of resolving timing differences down to 5ps [ ], however further improvement is impeded by process variations. This paper describes a flash TDC Time to Digital Converter (TDC) suitable for on-chip implementation. The theory to overcome the effects of process variations, potentially permitting the time resolution down to one picosecond is described. Proof of concept is demonstrated by implementing the techniques in an FPGA, improving on the current resolution of FPGA implementation of a TDC.
PublisherIEEE Computer Society
URLhttp://dx.doi.org/10.1109/ASYNC.2007.7
DOI10.1109/ASYNC.2007.7
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