Lookup NU author(s): Dr Yu Zhou,
Dr Danil Sokolov,
Professor Alex Yakovlev
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward way is to structurally map the gates in a synchronous netlist to their functionally equivalent modules which use delay-insensitive codes. Different trade-offs exist in previous methods between the overheads of the implementations and their robustness. The aim of this paper is to optimise the area of asynchronous circuits using partial acknowledgement concept. We employ this concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method. The benchmark results show the average reduction in area by 28% and in the number of inter-functional module wires that require timing verification by 67%, compared to NCL-X.
Author(s): Zhou Y, Sokolov D, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 2006 International Conference on Computer-Aided Design
Year of Conference: 2006
Publisher: ACM Press
Notes: IEEE/ACM International Conference on Computer Aided Design - Digest of Technical Papers.
Library holdings: Search Newcastle University Library for this item