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Combining Partial Orders and Symbolic Traversal for Efficient Verification of Asynchronous Circuits

Lookup NU author(s): Professor Alex Yakovlev

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Publication metadata

Author(s): Semenov A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: IFIP TC10 WG10.5 International Conference on Hardware Description Languages and Their Applications (CHDL)

Year of Conference: 1995

Pages: 567-573

Publisher: IEEE Press

URL: http://dx.doi.org/10.1109/ASPDAC.1995.486371

DOI: 10.1109/ASPDAC.1995.486371

Library holdings: Search Newcastle University Library for this item

ISBN: 4930813670


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