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Implementation of a phase-encoding signalling prototype chip

Lookup NU author(s): Crescenco D'Alessandro, Dr Alex Bystrov, Professor Alex Yakovlev

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Abstract

We report the results of the first prototype chip containing a silicon implementation of dual-rail phase-encoded links, where information is transmitted using the order of events on a pair of wires. The results show successful communication at bitrates exceeding 2 GB/s using standard-cell implementations on a 0.13μm technology. © 2008 IEEE.


Publication metadata

Author(s): D'Alessandro C, Bystrov A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 34th European Solid-State Circuits Conference (ESSCIRC 2008)

Year of Conference: 2008

Pages: 478-481

ISSN: 1930-8833

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ESSCIRC.2008.4681896

DOI: 10.1109/ESSCIRC.2008.4681896

Library holdings: Search Newcastle University Library for this item

ISBN: 9781424423620


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