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Dynamic Programming Networks for Large-Scale 3D Chip Integration

Lookup NU author(s): Dr Terrence Mak

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Abstract

Recent technological advance in three-dimensional (3-D) on-chip systems integration provides a promising platform to realize multicore, multiprocessor, and networks-on-chip (NoC) based systems with augmented performance. With the additional tightly coupled physical layers, on-chip system complexity grows significantly. The provision for efficient run-time management in large-scale system becomes critical. In this article, we review the design of an emerging on-chip dynamic-programming (DP) network, of which the capabilities have been demonstrated in a range of applications including optimal paths planning, dynamic routing and deadlock detection. A design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3-D) architecture using through-silicon-via (TSV) CMOS technology, is also presented. The vertical inter-layer communication is achieved by the means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. Testing results demonstrated the effectiveness of such approach for deadlock detection and the minuscule computational delay for detecting deadlock from a large-scale network.

Publication metadata

Author(s): Mak T, Al-Dujaily R, Zhou K, Lam K, Poon C

Publication type: Article

Publication status: Published

Journal: IEEE Circuits and Systems Magazine

Year: 2011

Volume: 11

Issue: 3

Pages: 51-62

Print publication date: 22/08/2011

ISSN (print): 1531-636X

ISSN (electronic): 1558-0830

Publisher: IEEE

URL: http://dx.doi.org/10.1109/MCAS.2011.942102

DOI: 10.1109/MCAS.2011.942102

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