Impact of Ge diffusion and wafer cross hatching on strained Si MOSFET electrical parameters

Driscoll, L; Olsen, S; Chattopadhyay, S; O'Neill, A; Kwa, K; Dobrosz, P; Bull, S

Impact of Ge diffusion and wafer cross hatching on strained Si MOSFET electrical parameters

Lookup NU author(s): Luke Driscoll, Dr Sarah Olsen, Dr Sanatan Chattopadhyay, Professor Anthony O'Neill, Dr Kelvin Kwa, Dr Piotr Dobrosz, Professor Steve Bull

Downloads

Full text for this publication is not currently held within this repository. Alternative links are provided below where available.

Abstract

A contender for future generations of CMOS technology is the strained silicon (S-Si) MOSFET. The mobility enhancement in S-Si can be exploited to maintain the performance enhancements demanded by Moore's law with reduced critical dimensions. S-Si is obtained by growth of a thin Si layer over a thick virtual substrate (VS) of relaxed silicon-germanium (SiGe). The mobility of a surface channel MOSFET is dependent on the quality of the silicon-oxide (Si/SiO2) interface. Ge may out diffuse from the virtual substrate to the oxide interface causing an increase in trapping density. As the Ge content in the virtual substrate increases surface roughness also increases. These phenomena both lead to a reduction in mobility. The study of a matrix of devices having variable Ge composition and S-Si thickness is crucial in deconvolving the contributions of Ge diffusion and wafer cross-hatching roughness on electrical parameters. Increasing VS Ge composition increases the Ge concentration at the SSi/SiO2 interface and cross-hatching amplitude whereas reducing S-Si channel thickness only increases Ge concentration at the S-Si/SiO2 interface and does not increase cross-hatch amplitude. Interface state density, drive current, gate leakage current, transconductance and carrier mobility data are presented for this two-dimensional space of VS composition and S-Si thickness. The relative importance of Ge diffusion and cross-hatching roughness can be seen in this data. The results of this study indicate a lower limit of 7 nm for the S-Si thickness and an upper limit of approximately 20% Ge in the virtual substrate for the current processing technology. Understanding the performance-limiting mechanisms in S-Si is crucial in the optimisation of VS Ge composition and S-Si thickness for current and future generations of S-Si CMOS.