Lookup NU author(s): Dr Frank Burns,
Dr Alex Bystrov,
Dr Albert Koelmans,
Professor Alex Yakovlev
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A new design flow for security is presented. Cryptographic circuit specifications are first refined and then mapped to a secure power-balanced library consisting of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Logic optimisation tools are then applied to generate secure synchronous circuits for layout generation. The circuits generated are more efficient than balanced circuits generated by alternative techniques. A new method is presented for evaluating the security of such circuits. A security metric is introduced, which is based on the common selection function that is widely used in differential power analysis (DPA) attacks and a correlation measure similar to the one used in correlation power analysis (CPA) attacks. The metric enables the construction of a library of robust cryptograhic components including S-boxes that are more resistant to attack.
Author(s): Burns F, Bystrov A, Koelmans A, Yakovlev A
Publication type: Article
Publication status: Published
Journal: IET Computers and Digital Techniques
Print publication date: 01/03/2012
ISSN (print): 1751-8601
ISSN (electronic): 1751-861X
Publisher: The Institution of Engineering and Technology
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