Lookup NU author(s): Abdullah Baz,
Dr Delong Shang,
Dr Fei Xia,
Professor Alex Yakovlev,
Dr Alex Bystrov
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
The most efficient power saying method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power saving requirements. A self-timed 6T SRAM was previously proposed, which adapts to the variable Vdd automatically. However due to leakage, the size of memory is restricted by process variations. This paper reports a new self-timed 10T SRAM cell with bit line keepers developed to improve robustness in order to work in a wide range of Vdds down to 0.3V under PVT variations. In addition, this paper briefly discusses the potential benefits of the self-timed SRAM for designing highly reliable systems and detecting the data retention voltage (DRV).
Author(s): Baz A, Shang DL, Xia F, Yakovlev A, Bystrov A
Editor(s): Ayala, J.L., Garcia Camara, B., Prieto, M., Ruggiero, M., Sicard, G.
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 21st International Workshop (PATMOS)
Year of Conference: 2011
ISSN: 0302-9743 (print) 1611-3349 (online)
Library holdings: Search Newcastle University Library for this item
Series Title: Lecture Notes in Computer Science