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Statistical Delay Modelling of Manufacturing Process Variations at System Level

Lookup NU author(s): Chenxi Ni, Dr Gordon Russell, Dr Alex Bystrov


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Process variation has become a major issue in system performance estimation as the technology feature size continues to decrease. This paper proposes a statistical methodology to bring the process variation effects from transistor level up to system level in terms of circuit delay. A cell library has been built which offers a rapid analysis of process variation effects on system delay performance. As a demonstration vehicle for this technique, the delay distribution of a micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method is much faster than the traditional SSTA approach by a factor of 50; the results are also compared with Monte Carlo simulation data for validation purposes, and show an acceptable error rate of within 5% and in most cases less than 3%.

Publication metadata

Author(s): Ni CX, Russell G, Bystrov A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 10th IEEE International New Circuits and Systems Conference (NEWCAS)

Year of Conference: 2012

Pages: 133-136

ISSN: 9781467308571

Publisher: IEEE


DOI: 10.1109/NEWCAS.2012.6328974

Library holdings: Search Newcastle University Library for this item

ISBN: 9781467308588


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