A Scalable FPGA-based Cerebellum for Passage-of-Time Representation

Luo, JW; Coapes, G; Mak, T; Yamazaki, T; Tin, C; Degenaar, P

doi:10.1109/EMBC.2014.6944279

A Scalable FPGA-based Cerebellum for Passage-of-Time Representation

Lookup NU author(s): Dr Jun Luo, Graeme Coapes, Dr Terrence Mak, Professor Patrick Degenaar

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Abstract

The cerebellum plays a critical role for sensorimotor control and learning. However dysmertria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. To foster a potential cure based on neuroprosthetic technology, we present a frame-based Network-on-Chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with 100,000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The results demonstrate that our implementation can reproduce the POT functionality properly. The computational speed can achieve to 25.6 ms for simulating 1 sec real world activities. Furthermore, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical applications.