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Lookup NU author(s): Professor Alex Yakovlev
As devices are scaled down and become faster while chips grow larger, a number of technological problems involving yield, power dissipation, wire delays versus gate delays, and so on, are being solved. A related set of VLSI design problems involve complexity, testing and timing. Of concern here are self-timed systems, that is, systems whose structure is an interconnection of self-timed modules communicating through asynchronous protocols without the use of a common clock. The self-timed design approach is capable of tackling the problems of design complexity, testing and timing.This article aims at reviewing the following: several approaches to self-timed VLSI design, examples of self-timed blocks and systems aired so far, and proposals for further steps in this area. Apart from this, one of the most important objectives of the article is to draw the designer's attention and manufacturer's attention to a design strategy that is very promising, although it has probably not yielded even a handful of demonstrated chip design examples to date.
Author(s): Yakovlev A
Publication type: Article
Publication status: Published
Journal: VLSI Systems Design
Year: 1985
Volume: VI
Issue: 9
Pages: 70-90
Print publication date: 01/09/1985
Date deposited: 02/11/2016
ISSN (print): 0887-9664
