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Signal graphs: a model for designing concurrent logic

Lookup NU author(s): Professor Alex Yakovlev

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Abstract

Asynchronous digital circuits exhibit a high degree of concurrency. Self-timed implementation is the most appropriate design discipline for them. We examine the signal graphs that are subject to formal treatment and mechanical translation to delay-insensitive circuits. An example of designing a piece of logic for typical interface adapter effectively illustrates the approach and sheds light on future work.


Publication metadata

Author(s): Kondratyev AYu, Rosenblum LYa, Yakovlev AV

Editor(s): Faye A. Briggs

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: International Conference on Parallel Processing (ICPP)

Year of Conference: 1988

Pages: 51-54

Print publication date: 15/08/1988

Date deposited: 02/11/2016

Publisher: Pennstate University Press

URL: http://dblp.org/rec/html/conf/icpp/KondratyevRY88

Library holdings: Search Newcastle University Library for this item

ISBN: 0271006544


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