Lookup NU author(s): Ammar Karkar,
Dr Terrence Mak,
Professor Alex Yakovlev
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and has satisfied different demands in terms of high performance and economical interconnect implementation. However, merely metal based NoC pursuit offers limited scalability with the relentless technology scaling, especially in one-to-many (1-to-M) communication. To meet the scalability demand, this paper proposes a new hybrid architecture empowered by both metal interconnects and Zenneck surface wave interconnects (SWI). This architecture, in conjunction with newly proposed routing and global arbitration schemes, avoids overloading the NoC and alleviates traffic hotspots compared to the trend of handling 1-to-M traffic as unicast. This work addresses the system level challenges for intra chip multicasting. Evaluation results, based on a cycle-accurate simulation and hardware description, demonstrate the effectiveness of the proposed architecture in terms of power reduction ratio of 4 to 12X and average delay reduction of 25X or more, compared to a regular NoC. These results are achieved with negligible hardware overheads. © 2014 EDAA.
Author(s): Karkar A, Dahir N, Al-Dujaily R, Tong K, Mak T, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Design, Automation and Test in Europe Conference and Exhibition (DATE 2014)
Year of Conference: 2014
Online publication date: 21/04/2014
Acceptance date: 01/01/1900
Library holdings: Search Newcastle University Library for this item