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Analytical evaluation of thermally oxidized and deposited dielectric in NMOS-PMOS devices

Lookup NU author(s): Dr Ming-Hung Weng, Idris Idris, Dr Hua Khee Chan, Dr Alton Horsfall

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Abstract

© 2016 Trans Tech Publications, Switzerland. We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1. The channel mobility extracted from n-and p-MOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm2V-1s-1, which are limited by the high doping level in the epilayers used in this study.


Publication metadata

Author(s): Weng MH, Idris MI, Chan HK, Murphy AE, Smith DA, Clark DT, Young RAR, Ramsay EP, Horsfall AB

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 16th International Conference on Silicon Carbide and Related Materials (ICSCRM2015)

Year of Conference: 2015

Pages: 631-634

Online publication date: 24/05/2016

Acceptance date: 03/01/2016

ISSN: 0255-5476

Publisher: Trans Tech Publications Ltd

URL: https://doi.org/10.4028/www.scientific.net/MSF.858.631

DOI: 10.4028/www.scientific.net/MSF.858.631

Library holdings: Search Newcastle University Library for this item

Series Title: Materials Science Forum

ISBN: 9783035710427


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