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Lookup NU author(s): Adrian Wheeldon,
Dr Jordan Morris,
Dr Danil Sokolov,
Professor Alex Yakovlev
This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2017.
For re-use rights please refer to the publisher's terms and conditions.
In this paper we present a self-timed, power proportional, 32-bit ripple-carry adder design using a state-of-the art cell library. The cell library implements a new transistor sizing strategy for subthreshold in a commercial 65 nm low power process. Simulation results show improvements in performance and energy per cycle when compared to a fixed-period design. The adder has applications in the internet of things where systems are required to operate over a wide range of conditions and with varying power supplies.
Author(s): Wheeldon A, Morris J, Sokolov D, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Year of Conference: 2017
Online publication date: 16/11/2017
Acceptance date: 04/07/2017
Date deposited: 07/12/2017
Library holdings: Search Newcastle University Library for this item