Lookup NU author(s): Oyinkuro Benafa,
Dr Danil Sokolov,
Professor Alex Yakovlev
This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2018.
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© 2018 IEEE. We present the decomposition and implementation of a loadable self-Timed counter that can perform seamless modulo loading and counting operation. The challenges in designing a loadable self-Timed counter stem from the need to dynamically reconfigure operations between the counter components to arrive at the desired count modulo. The counter was decomposed into a combination of parallel and interacting computing cells as presented by Kessels. The binary equivalent for the count modulo n determined the operation of each cell in relation to its significance. Specification and verification of the counter are by formal asynchronous design methods employing Petri Nets. A 5-bits loadable counter is implemented and fabricated in 350nm CMOS process. Average power consumed at 3.3V for count 31 is in the range 89IW to 157IW. The response time of the counter after a load request is received ranges from 28.80ns to 32.71ns. Such a counter is robust and presents a practical application in timing systems like the Digital Pulse Width Modulator~(DPWM) used in a DC-DC converter with fine tune control. For example, the DPWM design can sustain a variation of Vdd in the range of 3.3V to 1.8V maintaining its duty-cycle with a margin of error in the range of 1% to 7%.
Author(s): Benafa O, Sokolov D, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Year of Conference: 2018
Online publication date: 27/12/2018
Acceptance date: 02/04/2018
Date deposited: 08/03/2019
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