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Design and Analysis of High Mobility Enhancement Mode 4H-SiC MOSFETs Using a Thin SiO2 / Al2O3 Gate Stack

Lookup NU author(s): Dr Jesus Urresti Ibanez, Dr Sarah Olsen, Professor Nick Wright, Professor Anthony O'Neill

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This is the authors' accepted manuscript of an article that has been published in its final definitive form by IEEE, 2019.

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Abstract

High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm2/V · s, and a peak field effect mobility of 154 cm2/V s, in 2-μmgate lengthMOSFETs. The gate-stackwas designed to minimize interface states and comprised a 0.7-nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of 6 × 1011–5 × 1010cm−2eV−1 is also obtained. Temperature-dependentelectrical data reveal that the high mobility results from conduction being phononlimited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of −4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.


Publication metadata

Author(s): Urresti J, Arith F, Olsen S, Wright N, ONeill A

Publication type: Article

Publication status: Published

Journal: Transactions on Electron Devices

Year: 2019

Volume: 66

Issue: 4

Pages: 1710-1716

Print publication date: 01/04/2019

Online publication date: 06/03/2019

Acceptance date: 20/02/2019

ISSN (print): 0018-9383

ISSN (electronic): 1557-9646

Publisher: IEEE

URL: http://doi.org/10.1109/TED.2019.2901310

DOI: 10.1109/TED.2019.2901310


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