Optimisation of the gate voltage in SiC MOSFETs: Efficiency vs reliability

Gonzalez, JO; Wu, R; Wu, H; Wang, X; Pickert, V; Mawby, P; Alatise, O

doi:10.1049/icp.2021.1043

Optimisation of the gate voltage in SiC MOSFETs: Efficiency vs reliability

Lookup NU author(s): Dr Haimeng Wu, Dr Xiang Wang, Professor Volker Pickert, Layi Alatise

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Abstract

© PEMD 2020. All right reserved. This paper presents a comprehensive study of the impact of the gate voltage on the switching and ON-state performance of SiC MOSFETs. It is well known that the gate oxide in SiC MOSFETs is not as reliable as that in silicon MOSFETs due to increased fixed oxide and interface traps. Numerous studies have shown reduced performance on time-dependent dielectric breakdown (TDDB) and oxide robustness in SiC MOSFETs compared to silicon devices. On the one hand, a high ON-state gate-source voltage VGS is required for proper channel inversion, low ON-state loss and fast switching while on the other hand, a lower ON-state VGS reduces the electrical stress on the gate oxide and improves long term reliability. Understanding the implications of the selected gate voltage on the operation of the power device will be fundamental for achieving an optimal balance between electrical performance and gate oxide reliability. This paper shows that reducing the maximum gate driver supply voltage VGG only affects turn-ON losses while turn-OFF losses are independent of VGG. The experimental characterisation is complemented with electrothermal simulations to evaluate the impact of the gate voltage on the operation of a converter. The paper shows that reducing VGG by 10% causes an increase of 7.6 % in the device losses and 1.4 °C in junction temperature in simulated converter operation. Furthermore, if the switching speed is increased by means of reducing the gate resistance, the impact of the conduction losses can be compensated. These results are fundamental for balancing system efficiency and reliability in SiC MOSFETs.