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Power-delay-area efficient modulo 2n+1adder architecture for RNS

Lookup NU author(s): Professor Said Boussakta

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Author(s): Patel R, Benaissa M, Boussakta S, Powel P

Publication type: Article

Publication status: Published

Journal: Electronics Letters

Year: 2005

Volume: 41

Issue: 5

Pages: 35-36

ISSN (print): 0013-5194

ISSN (electronic): 1350-911X

Publisher: The Institution of Engineering and Technology

URL: http://dx.doi.org/10.1049/el:20056837

DOI: 10.1049/el:20056837

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