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Off-line testing of asynchronous circuits

Lookup NU author(s): Deepali Koppad, Dr Alex Bystrov, Professor Alex Yakovlev

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Abstract

A new technique to test asynchronous circuits obtained by direct mapping technique from I-safe Petri nets is proposed. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into high-level specification, a Petri net. A "pseudo clock" is used to handle hazards and activate faults which exhibit themselves only under particular arrangements. Asynchronous circuit obtained by direct mapping technique can be made 100% testable for stuck-at-faults by implementing testability features. An algorithm to insert testability features and generate test sequences is presented using a benchmark. (14 References).


Publication metadata

Author(s): Koppad D, Bystrov A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 18th International Conference on VLSI Design

Year of Conference: 2005

Pages: 730-5

ISSN: 9780769522647

Publisher: IEEE Computer Society

Library holdings: Search Newcastle University Library for this item

ISBN: 0769522645


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