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Synthesis of asynchronous hardware from Petri nets

Lookup NU author(s): Dr Victor Khomenko, Professor Alex Yakovlev

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Abstract

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits from large Petri nets generated from front-end specifications in hardware description languages. These new methods avoid using full reachability state space for logic synthesis. They include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers. (78 References).


Publication metadata

Author(s): Carmona J, Cortadella J, Khomenko V, Yakovlev A

Editor(s): Desel, J., Reisig, W., Rozenberg, G.

Publication type: Book Chapter

Publication status: Published

Book Title: Lectures on Concurrency and Petri Nets: Advances in Petri Nets

Year: 2004

Volume: 3098

Pages: 183-205

Series Title: Lecture Notes in Computer Science

Publisher: Springer

Place Published: Berlin

URL: http://dx.doi.org/10.1007/978-3-540-27755-2_9

DOI: 10.1007/978-3-540-27755-2_9

Notes: Desel J Reisig W Rozenberg G Berlin, Germany.

Library holdings: Search Newcastle University Library for this item

ISBN: 9783540222613


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