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Modelling, analysis and synthesis of asynchronous control circuits using Petri nets

Lookup NU author(s): Professor Alex Yakovlev, Dr Albert Koelmans, Professor David Kinniment

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Abstract

In this tutorial paper we survey some of the existing techniques for modelling, analysis and synthesis of asynchronous control circuits. All these methods are based on the use of Petri nets as a tool for describing the behaviour of such circuits. The descriptive power of Petri nets allows them to model a wide range of asynchronous circuit components, whether they are built in the two-phase (micropipeline) or in the four-phase (logic gate based) design styles. We present three different approaches to verification of net-based models, and show their relative strengths and weaknesses. We advocate their complementary application for different classes of Petri nets and the properties verified. Two major synthesis approaches are demonstrated using the example of a modulo-N Up/Down counter. The first one is a combination of Petri net level decompositions and syntax-directed translation of nets into circuits. The second one is based on logic synthesis from signal transition graph specifications.


Publication metadata

Author(s): Yakovlev AV, Koelmans AM, Semenov A, Kinniment DJ

Publication type: Article

Publication status: Published

Journal: Integration: the VLSI journal

Year: 1996

Volume: 21

Issue: 3

Pages: 143-170

Print publication date: 01/12/1996

ISSN (print): 0167-9260

ISSN (electronic): 1872-7522

Publisher: Elsevier

URL: http://dx.doi.org/10.1016/S0167-9260(96)00010-7

DOI: 10.1016/S0167-9260(96)00010-7


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