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Logic decomposition of speed-independent circuits

Lookup NU author(s): Professor Alex Yakovlev

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Abstract

Logic decomposition is A well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of A gate into smaller gates must preserve not only the functional correctness of A circuit but Also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents A new method for logic decomposition of speed-independent circuits that solves the problem in firo major steps: 1) logic decomposition of complex gates And 2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous Approaches And its effectiveness is evaluated by experiments on A set of benchmarks. © 1999 IEEE.


Publication metadata

Author(s): Kondratyev A, Cortadella J, Kishinevsky M, Lavagno L, Yakovlev A

Publication type: Article

Publication status: Published

Journal: Proceedings of the IEEE

Year: 1999

Volume: 87

Issue: 2

Pages: 347-362

Print publication date: 01/01/1999

ISSN (print): 0018-9219

ISSN (electronic): 1558-2256

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/5.740027

DOI: 10.1109/5.740027


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