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Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions

Lookup NU author(s): Professor Alex Yakovlev

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Abstract

This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. Lazy transition systems can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents necessary conditions to generate circuits and a synthesis algorithm that exploits the timing assumptions for optimization. It also proposes a method for back-annotation that derives a set of sufficient timing constraints that guarantee the correctness of the circuit.


Publication metadata

Author(s): Cortadella J, Kishinevsky M, Burns SM, Kondratyev A, Lavagno L, Stevens KS, Taubin A, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2002

Volume: 21

Issue: 2

Pages: 109-130

Print publication date: 01/02/2002

ISSN (print): 0278-0070

ISSN (electronic): 1937-4151

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/43.980253

DOI: 10.1109/43.980253


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