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Design of asynchronous controllers with delay insensitive interface

Lookup NU author(s): Hiroshi Saito, Professor Alex Yakovlev

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Abstract

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (Dl), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally Dl and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that Dl interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).


Publication metadata

Author(s): Saito H, Kondratyev A, Cortadella J, Lavagno L, Yakovlev A, Nanya T

Publication type: Article

Publication status: Published

Journal: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Year: 2002

Volume: E85-A

Issue: 12

Pages: 2577-2585

Print publication date: 01/12/2002

ISSN (print): 0916-8508

ISSN (electronic): 1745-1337

Publisher: Denshi Jouhou Tsuushin Gakkai


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