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Improving the security of dual-rail circuits

Lookup NU author(s): Dr Danil Sokolov, Dr Julian Murphy, Dr Alex Bystrov, Professor Alex Yakovlev

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Abstract

Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e. g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method. © International Association for Cryptologic Research 2004.


Publication metadata

Author(s): Sokolov D, Murphy J, Bystrov A, Yakovlev A

Publication type: Book Chapter

Publication status: Published

Book Title: Cryptographic Hardware and Embedded Systems - CHES 2004

Year: 2004

Volume: 3156

Pages: 282-297

Print publication date: 01/01/2004

Series Title: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Publisher: Springer

Place Published: Berlin

URL: http://dx.doi.org/ 10.1007/978-3-540-28632-5_21

DOI: 10.1007/978-3-540-28632-5_21

Library holdings: Search Newcastle University Library for this item

ISBN: 9783540226666


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