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Design and analysis of a self-timed duplex communication system

Lookup NU author(s): Professor Alex Yakovlev, Rene Krenz, Dr Alex Bystrov

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Abstract

Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs will be more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal transition on a global interconnect is much greater than for internal wires in logic blocks. The paper addresses this issue by designing an asynchronous communication system aimed at power and pin efficiency. Another important issue of SoC design is design productivity. It demands new methods and tools, particularly for designing communication protocols and interconnects. The design of a self-timed communication system is approached employing formal techniques supported by verification and synthesis tools. The protocol is formally specified and verified with respect to deadlock-freedom and delay-insensitivity using a Petri-net-based model-checking tool. A protocol controller has been synthesized by a direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analyzed using the Cadence toolkit. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis. © 2004 IEEE.


Publication metadata

Author(s): Yakovlev A, Furber S, Krenz R, Bystrov A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computers

Year: 2004

Volume: 53

Issue: 7

Pages: 798-814

Print publication date: 01/07/2004

ISSN (print): 0018-9340

ISSN (electronic): 1557-9956

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/TC.2004.26

DOI: 10.1109/TC.2004.26


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