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Optimisation of a 4H-SiC enhancement mode power JFET for high temperature operation

Lookup NU author(s): Praneet Bhatnagar, Dr Alton Horsfall, Professor Nick Wright, Dr Christopher Johnson, Dr Konstantin Vasilevskiy, Professor Anthony O'Neill

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Abstract

We present the optimization of an enhancement mode vertical channel junction field effect transistor (VJFET), by investigating the variation of the controlled power density (the product of the on-state current density and the forward blocking voltage) of the device on both the source finger width and temperature. It is shown that a reduction in the source finger width is required to maximize this switch VA as the ambient temperature is increased. The structure considered has a varying finger width of 2.1 μm for operation at 300 K, which falls to 1.9 μm at 700 K. This reduction in finger width is related to the reduction in blocking voltage as the temperature is increased due to the reduction in the built in potential of the p-n junction used to form the gate. We show that a device with a finger with of 1.9 μm is optimal across the temperature range studied, due to the maintenance of the forward blocking voltage at approximately 1200 V. The reduction in the controlled power density as the temperature increases is linked to the drop in forward current density of the device. © 2004 Elsevier Ltd. All rights reserved.


Publication metadata

Author(s): Bhatnagar P, Horsfall AB, Wright NG, Johnson CM, Vassilevski KV, O'Neill AG

Publication type: Article

Publication status: Published

Journal: Solid-State Electronics

Year: 2005

Volume: 49

Issue: 3

Pages: 453-458

ISSN (print): 0038-1101

ISSN (electronic): 1879-2405

Publisher: Pergamon

URL: http://dx.doi.org/10.1016/j.sse.2004.12.002

DOI: 10.1016/j.sse.2004.12.002


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