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Test chip for the development and evaluation of sensors for measuring stress in metal interconnects

Lookup NU author(s): Dr Alton Horsfall, Sorin Soare, Professor Nick Wright, Professor Anthony O'Neill, Professor Steve Bull

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Abstract

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes. © 2005 IEEE.


Publication metadata

Author(s): Terry JG, Smith S, Walton AJ, Gundlach AM, Stevenson JTM, Horsfall AB, Wang K, Dos Santos JMM, Soare SM, Wright NG, O'Neill AG, Bull SJ

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Semiconductor Manufacturing

Year: 2005

Volume: 18

Issue: 2

Pages: 255-260

Date deposited: 09/12/2010

ISSN (print): 0894-6507

ISSN (electronic): 1476-5527

Publisher: IEEE

URL: http://dx.doi.org/10.1109/TSM.2005.845096

DOI: 10.1109/TSM.2005.845096


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