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Design and analysis of dual-rail circuits for security applications

Lookup NU author(s): Dr Danil Sokolov, Dr Julian Murphy, Dr Alex Bystrov, Professor Alex Yakovlev

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Abstract

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool. © 2005 IEEE.


Publication metadata

Author(s): Sokolov D, Murphy J, Bystrov A, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computers

Year: 2005

Volume: 54

Issue: 4

Pages: 449-460

Print publication date: 01/04/2005

ISSN (print): 0018-9340

ISSN (electronic): 1557-9956

Publisher: IEEE

URL: http://dx.doi.org/10.1109/TC.2005.61

DOI: 10.1109/TC.2005.61


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