Lookup NU author(s): Sohini Dasgupta,
Professor Alex Yakovlev
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We consider the problem of synthesizing the asynchronous wrappers and glue logic needed for the correct GALS implementation of a modular synchronous system. Our approach is based on the weakly endochronous synchronous model, which defines high-level, implementation-independent conditions guaranteeing correct desynchronization at the level of the abstract synchronous model. We can therefore factor the synthesis problem into (1) a high-level, implementation-independent phase insuring the weak endochrony of each synchronous module and (2) the actual wrapper synthesis phase, highly simplified by the high-level assumptions, yet flexible enough to produce various, efficient implementations. We focus here on the synthesis of delay-insensitive asynchronous wrappers from weakly endochronous synchronous modules, and show how this can be done for a simple DLX processor model. © 2006 Elsevier B.V. All rights reserved.
Author(s): Dasgupta S, Potop-Butucaru D, Caillaud B, Yakovlev A
Publication type: Article
Publication status: Published
Journal: Electronic Notes in Theoretical Computer Science
ISSN (print): 1571-0661
Publisher: Elsevier BV
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