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Modeling and performance analysis of GALS architectures

Lookup NU author(s): Professor Alex Yakovlev

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Abstract

In this paper we present a comparison of three clock control schemes and how it can be applied to an exisiting partitioned synchronous architecture to obtain a reliable, low latency and efficient Globally Asynchronous and Locally Synchronous architectures. The comparison highlights the advantages and disadvantages of one scheme over the other in terms of logical correctness, circuit implementation, performance and relative power consumption. We also present here circuit solutions for stretchable and data driven clocking schemes. These circuit solutions can be easily plugged into existing partitioned synchronous islands. To enable early evaluation of functional correctness, this paper proposes the use of Petri net modeling technique to model the asynchronous control blocks that constitute the interface between the synchronous islands. © 2006 IEEE.


Publication metadata

Author(s): Dasgupta S, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2006 International Symposium on System-on-Chip, SOC

Year of Conference: 2006

Pages: 1-4

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ISSOC.2006.321998

DOI: 10.1109/ISSOC.2006.321998

Library holdings: Search Newcastle University Library for this item

ISBN: 1424406226


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