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Direct mapping of low-latency asynchronous controllers from STGs

Lookup NU author(s): Dr Danil Sokolov, Dr Alex Bystrov, Professor Alex Yakovlev

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Abstract

A method for an automated synthesis of low-latency asynchronous controllers is presented. It is based on a direct mapping approach and starts from an initial specification in the form of a signal transition graph (STG). This STG is split into a device and an environment, which synchronize via a communication net that models wires. The device is represented as a tracker and a bouncer. The tracker follows the state of the environment and provides reference points to the device outputs. The bouncer communicates with the environment and generates output events in response to the input events according to the state of the tracker. This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist. A set of optimization heuristics is developed to reduce the latency and size of the circuit. As a result of this paper, a software tool called OptiMist has been developed. Its low algorithmic complexity allows large specifications to be synthesized, which is not possible for the tools based on state-space exploration. OptiMist successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route. © 2007 IEEE.


Publication metadata

Author(s): Sokolov D, Bystrov A, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2007

Volume: 26

Issue: 6

Pages: 993-1009

Print publication date: 01/06/2007

ISSN (print): 0278-0070

Publisher: I E E E

URL: http://dx.doi.org/10.1109/TCAD.2006.884416

DOI: 10.1109/TCAD.2006.884416


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