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The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk

Lookup NU author(s): Dr Basel Halak, Santosh Shedabale, Professor Alex Yakovlev, Dr Gordon Russell

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Abstract

With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability. Copyright 2008 ACM.


Publication metadata

Author(s): Halak B, Shedabale S, Ramakrishnan H, Yakovlev A, Russell G

Editor(s): ACM Special Interest Group on Design Automation

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: International Workshop on System Level Interconnect Prediction, SLIP

Year of Conference: 2008

Pages: 65-72

Publisher: IEEE Computer Society

DOI: 10.1145/1353610.1353624

Library holdings: Search Newcastle University Library for this item

ISBN: 9781595939180


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