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On-chip structures for timing measurement and test

Lookup NU author(s): Professor David Kinniment, Dr Oleg Maevsky, Dr Alex Bystrov, Dr Gordon Russell, Professor Alex Yakovlev

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Abstract

This paper describes the use of digitally set delay lines in conjunction with MUTEX time comparison circuits, to measure on-chip signal path timing differences to accuracies of better than 10ps. Three methods of time measurement are described. The first, which uses parallel MUTEXs with a tapped delay line, is analogous to a flash AID converter. The second one is similar to a successive approximation method. Both are fast, and efficient, but the second requires less hardware for a large number of bits. The third technique uses a MUTEX to amplify small time differences to a measurable size. Applications for these techniques include adaptive synchronization and input tests, such as data set-up time conditions that currently require the use of very expensive test hardware. We describe an on-chip method of testing these conditions, using uncorrelated signals whose statistics are known, and accurately selecting the conditions to be tested on-chip. (8 References).


Publication metadata

Author(s): Kinniment DJ, Maevsky OV, Bystrov A, Russell G, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Conference Name: 8th International Symposium on Asynchronous Circuits and Systems (ASYNC 2002)

Year of Conference: 2002

Pages: 190-197

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/ASYNC.2002.1000309

DOI: 10.1109/ASYNC.2002.1000309

Notes: Los Alamitos, CA, USA. Proceedings Eighth International Symposium on Asynchronous Circuits and Systems. Manchester, UK. IEEE Comput. Soc. Tech. Committee on VLSI. 8-11 April 2002.

Library holdings: Search Newcastle University Library for this item

ISBN: 0769515401


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